Abstract:
Microprocessors are the devices in a computer that make things happen. They are capable of performing basic arithmetic operations, moving data from place to place, and making basic decisions based on the quantity of certain values. In this project a systematic step of designing of microprocessor from the ground up methodology has been described. To define the behavior of the Complex Programmable Logic Devices (CPLDs), a description of the hardware's structure and behavior was written in a High-level Hardware Description Language (VHDL) and that code was then compiled and downloaded prior to execution. The design entry step is followed or interspersed with periods of functional simulation using QuartusII software. That's where a simulator is used to execute the design and confirm that the correct outputs are produced for a given set of test inputs.
Compilation only begins after a functionally correct representation of the hardware exists. This hardware compilation consists of two distinct steps. First, an intermediate representation of the hardware design was produced. This step is called synthesis and the result of a representation called a netlist. The netlist is device independent, so its contents do not depend on the particulars of the FPGA or CPLD; it is usually stored in a standard format called the Electronic Design Interchange Format (EDIF). The second step in the translation process is called place & route. This step involves mapping the logical structures described in the netlist onto actual macrocells, interconnections, and input and output pins; this is the bitstream format.
Once the bitstream has been created a CPLD kit (ALTERA kit) was used to check the designed microprocessor performance. The generated bitstream was downloaded into max EPM7128SLC84-7.
