Please use this identifier to cite or link to this item: https://repository.sustech.edu/handle/123456789/8068
Title: Cyclic Redundancy Check Error Detection Circuit Design
Authors: Albadawy, Mogahid Omer Hajeltoum
Supervisor - Abdelrasoul Jabar AlzubaidiAbdelrasoul
Keywords: Computer Engineering
Circuit
Circuit - Design
Issue Date: 1-Sep-2005
Publisher: Sudan University of Science & Technology
Citation: Albadawy, Mogahid Omer Hajeltoum .Cyclic Redundancy Check Error Detection Circuit Design/Mogahid Omer Hajeltoum Albadawy;Abdelrasoul Jabar AlzubaidiAbdelrasoul.-Khartoum:Sudan University of Science & Technology,College of Engineering,2006.-58P. : ill. ; 28Cm.-M.Sc.
Abstract: Binary information "bits" are at the heart of modern communications. All information can be represented as blocks of stream of bits. Modern communication networks are designed to carry bits and therefore they can handle any type of information CRC is the most powerful error detection more than parity bit and check sum method, cause it can be used to detect single bit error, two bits error and burst error. CRC calculation require a divisor which called sometimes "Generator polynomial" or "poly". The width of poly is very important as dominate the whole calculation, typically width of 8 or 16 or 32 are chosen so as to simplify implementation on modern computers. The width of the poly is actual one bit more on most significant bit. Any transmitted message T is attached with remainder after dividing the original message this remainder called CRC. The receiver divide the received message into some poly that used at the transmitter the remainder must be zero, which means that there is no error at received message.
Description: Thesis
URI: http://repository.sustech.edu/handle/123456789/8068
Appears in Collections:Masters Dissertations : Engineering

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