DYNAMIC RANDOM ACCESS MEMORY ADDRESS DECODING

Abstract

Dynamic Random Access Memories (DRAM) is the dominant solid-state memory devices used for primary memories in the ubiquitous microprocessor systems of today. In recent years, processor frequencies have grown at high rate per year, while DRAM latencies have improved at low rate per year. This growing gap has been referred to as the “Memory Wall.” DRAM architectures have been going through rapid changes in order to reduce the performance impact attributable to this increasing relative latency of primary memory accesses. This thesis examines conventional DRAM architectures.

The framework for DRAM implementations, based on a number of perspectives and criteria. Reading, writing and refreshing cycles are major components of the DRAM working. The hardware project used to examining the underlying performance enhancing characteristics of DRAM. An important contribution of this work is identification and examination of a set of characteristics, which try to determine the DRAM system performance. The intent of this thesis is examining DRAM architectures and performance

the circuit design contains two section, the first one work instead of DRAM controller that not available in the local market, then we use 74273 latch register that work at up-edge, further more, we add the transparent latch 74373 to eliminate the conflict due to the read-write operation from/to the DRAM, and the second circuit contains DRAM TMS4416.The experiment results taken from the practical circuit operation in conformity with the program results shown.