Read only memory for multiplier design based on FPGA

Abstract

The Spartan-3 family of Field-Programmable Gate Arrays (FPGA) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to five million system gates. This project describes Read only memory(256addressx8bits) based on FPGA for multiplier design for high speed and low power. Read only memory (ROM) design can be generated by creating an array and filling it with the data values (Nubble * Nubble of address). an array is defined with a size (number of elements) equal to the number of address locations in the memory. This has 256 address locations and 8 data bits per address.The array is filled with values in the Constant data object. The Data output is assigned the value held within selected element of the Rom_Array. The Address input selects the array element to access. The Address here is an integer data type with values from 0 to 255. the processing method to construct the design. implements VHDL to describe the design, Synopsys tools to synthesize it and Xilinx tools to target the design . VHDL coding style, a high level synthesis strategy and the methodologies of FPGA design are briefly discussed.