Please use this identifier to cite or link to this item: https://repository.sustech.edu/handle/123456789/11160
Title: Servo- Motor Control Using Phase Locked Loop
Other Titles: تحكم المحرك المؤازر باستخدام حلقة الطور المغلقة
Authors: Babkir, Ahmed Abdalla Ahmed
Supervisor - Abdalla Salih Ali
Keywords: Electrical Engineering
Control and Microprocessor
Servo-motor
Issue Date: 1-Apr-2015
Publisher: Sudan University of Science and Technology
Citation: Babkir ,Ahmed Abdalla Ahmed .Servo- Motor Control Using Phase Locked Loop /Ahmed Abdalla Ahmed Babkir ;Abdalla Salih Ali .-khartoum :Sudan University of Science and Technology,COLLEGE OF Engineering,2015 .-42p. :ill ;28cm .-M.Sc.
Abstract: The speed regulation of servo motor can be improved by using phase locked loop. The speed of motor must be converted to digital pulse train using a speed encoder. The output of the encoder acts as speed feedback signal. A phase detector is used to compare the reference pulse with feedback frequency and provide a Pulse Width Modulation (PWM) output voltage which is proportional to the difference in phases and frequencies of reference and feedback pulse trains. The phase detector (or comparator) is available in integrated circuits. A low-pass filter converts the pulse trains to continuous dc level which varies the output of the power converter and in turn the motor speed. When the motor runs at the same speed as the reference pulse the two frequencies would be synchronized or locked together with a phase difference. The output of the phase detector would be constant voltage proportional to the phase difference and the steady-state motor speed would be maintained at a fixed value irrespective of the load on the motor. Any disturbances contributing the speed change would result in a phase difference and the output of the phase detector would respond immediately to vary the speed of the motor in such a direction and magnitude as to retain the locking of the reference and feedback frequencies. The response of the phase detector is very fast. As long as the two frequencies are locked, the speed regulation should ideally be zero. However, in practice the speed regulation is limited to 0.002%, and this represents a significant improvement over the analog speed control system.
Description: Thesis
URI: http://repository.sustech.edu/handle/123456789/11160
Appears in Collections:Masters Dissertations : Engineering

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