Abstract:
A digital down converter is one of the main parts of the software defined radio, to enable driving the signal from antenna to the baseband processing which was till the recent past too difficult due to less reliability of processing and analog circuitry. Nowadays high frequency processing is in demand with the appearance of FPGA, and ASIC. The digital and very high speed processing have become more available.
In this thesis full design and simulation of the digital down converter (DDC) is done. The simulation took two paths, MATLAB path and VHDL path. In the MATLAB path SIMULINK blocks were used to represent the DDC parts, two quadrature signals with very high data rate (about 140 Mbps) inputs to the DDC mixer, then numerically controlled oscillator (NCO) block parameters were set to generate an appropriate local oscillator (LO) frequency and mixed with the quadrature signals to get suitable intermediate frequency, Then a chain of FIR CIC filters is used to down convert the high rate and separate the base band signal.
The VHDL path follows the MATLAB model. In Xilinx SIMULINK block set, the system generator block is used to convert MATLAB model to VHDL code, Test bench file is generated and modified to satisfy the design parameters. Compilation and simulation of the code have been done.
The final signal information and data rate obtained from the MATLAB has been compared to VHDL results, The input RF signal was 299 Mhz and after DDC is become 675 Khz and the sample rate was down converted from 140 Mbps to 2.187 Mbps and the compared results were identical.
