On chip communication Architecture Power Estimation in High Frequency

Abstract

The development in embedded system on chip SoC is still evolving in its capabilities, to cover the everlasting needs in high edge technology over the world production and manufacturing, the development led to a plethora of SoC chip designs having high processing capabilities with high memory and interfaces all of this requirements increased the consumed power within the chip, bearing this in mind, we find all system designers over the world are optimizing power usage efficiency over the system chip due to its low power budget usage (E.g. batteries), based on all of this we find that a good power optimization system must be built over an accurate power estimation scheme. This thesis proposes a power SoC estimation based on a system level analysis for a commercial piece of the art ARM Bus Architecture (AMBA chip), and that by decomposing the SoC chip power to the power consumed in (i) the logic element such as (arbiter, decoder, input devices and output devices) which called system devices which will be calculated by taking any device functionality in consideration such as (control signal and transitions), (ii) the chip bus and bus interface by developing a high frequency model using RLC component calculation for the bus wire, by bearing in mind system activity we use high level power model which presume that the bus power is consumed in the VIAS, the repeaters and the switching power, by implying these methods to the matlab we generated a power spectrum estimation in all system parts individually, by comparing the consumed power magnitude and amplitude in the system deferent parts we can understand the power consumption level which can help the designer in system evaluation and power optimization, it can be seen that using this method give us a hole on chip communication power estimation.