Design of an Efficient Cyclic Redundancy Check-32 using Field Programmable Gate Array

Abstract

The streaming of data over the networks is increasing day by day. the current applications, video web sites, Internet of things and Machine to Machine made new era of the data over the internet.Accordingly, the networking devices should be evolved to meet this change. the hardware and the software needs continuously to be upgraded and the research in this area cannot be stopped. Part of this research area is the cyclic redundancy check (CRC) which is the error detection technique that used for data integrity. The exist CRC32 that being implemented on the networking devices cannot meet the high speed requirements which is expected to 100 Gbps in the core, aggregation and backbone networking devices such as routers and switches. So the aim of this research is to perform a design of CRC32 capable to achieve a throughput equal to 100 Gbps. The design of the CRC32 performed using slicing by 16 algorithm that synthesized in Xilinx Virtex-7 Field Programmable Gate Array (FPGA) and simulated by Xilinx Isim. The result show that the achieved throughput is equal to 102.4 Gbps.